1. Field of the Invention
The present invention relates to a power supply circuit and an electronic device equipped with the power supply circuit and more particularly to the power supply circuit made up of single and conductive-type (n-type or p-type) MOS transistors and suitably used as a DC/DC converter to convert a supplied DC (Direct Current) input voltage into a DC output voltage at a given level, in particular and the electronic device equipped with the power supply circuit.
2. Description of the Related Art
As the power supply circuit made up of semiconductors, a charge-pump circuit consisting of an electronic switch having transistors and capacitors is available. The charge-pump circuit, owing to integration of its electronic switch using a semiconductor transistor, thin film transistor, or a like, can be made small and lightweight and, therefore, can be widely used for a portable electronic device such as a portable phone, notebook personal computer, or a like. As a circuit making up the semiconductor device, generally, a CMOS (Complementary MOS) circuit having an n-type MOS (hereinafter simply “nMOS”) transistor and a p-type MOS (hereinafter simply “pMOS”) transistor is used in many cases since the CMOS circuit consumes less power. However, there are problems in that, when a semiconductor device using CMOS circuits is to be manufactured, in addition to processes of deposition, mask exposure, etching, or a like, a plurality of times of impurity implantation processes to fabricate the pMOS and nMOS is required, which causes the manufacturing process to be complicated.
On the other hand, in the case of the semiconductor device made up of only single and conductive-type MOS transistors including the pMOS or nMOS transistors, it is possible to reduce the number of processes such as an impurity implantation process, thereby making the manufacturing processes comparatively simple. However, if the semiconductor device is made up of only the single and conductive-type MOS transistors, another problem arises that the single and conductive-type MOS transistors consume more power than the CMOS transistors and a noise margin of the single and conductive-type MOS transistor is low and its output margin is made to be decreased. To solve these problems, an improved semiconductor is proposed.
A conventional technology of this type is disclosed in Patent Reference 1 (Japanese Patent No. 3040885, page 3, FIG. 6). The power supply circuit disclosed in the Patent (referred to as a “voltage boosting circuit” in the Patent), as shown in FIG. 18, includes nMOS transistors MT5A, MT1A, MT2A, MT3A, MT4A, MT6A, MT7A, MT5B, MT1B, NT2B, MT3B, MT4B, MT6B, and MT7B and capacitors C0A, C1A, C2A, C3A, C4A, C5A, C0B, C1B, C2B, C3B, C4B, and C5B. The disclosed power supply circuit is a circuit to generate, by using a DC input voltage and clocks CLKA and CLKB being opposite in phase to each other, a DC output voltage [VOUT] whose potential is higher than that of the DC input voltage [VDD].
In the disclosed voltage boosting circuit, in synchronization with transition of a potential of each of the clocks CLKA and CLKB from its low level [VSS (=0V)] to its high level [VDD] or from its high level [VDD] to its low level [VSS], each of the nMOS transistors gets into an ON state or an OFF state. That is, when the clock CLKA has the low potential [VSS] and the clock CLKB has the high potential [VDD], ideally, each of the nMOS transistors MT5A, MT1B, MT2A, MT3B, MT4A, MT6B, and MT7A gets into the ON state, while each of the nMOS transistors MT5B, MT1A, MT2B, MT3A, MT4B, MT6A, and MT7B gets into the OFF state. At this time point, the node N0A is charged so that its potential is lower by a gate threshold voltage [Vth] of the nMOS transistor MT5A than the DC input voltage [VDD], that is, the potential at the node N0A becomes a potential [VDD-Vth]. Moreover, the potential at the node N0B, due to the transition of the potential of the clock CLKB to the high potential [VDD], is boosted to the potential [2×VDD-Vth]. Since the nMOS transistor MT1B is in an ON state, the potential at the node N1B is at the same level as the node N0B.
Next, when the potential of the clock CLKA is changed to be a high potential [VDD], since the capacitor has been already charged so as to have the voltage [VDD-Vth], the potential of the node N0A is boosted to the level [VDD-Vth+VDD=2×VDD-Vth] and if the nMOS transistor MT1A is in the ON state, the potential of the node N1A is also boosted to the level [2×VDD-Vth]. Similarly, the potential at the node N1B is boosted from the level [2×VDD-Vth] to the level [3×VDD-Vth]. Thereafter, the potential at each of the nodes is sequentially boosted and, ideally, the DC output voltage [VOUT] is boosted to a level [6×VDD-Vth].
However, the above conventional power supply circuit has the following problems. Even in a period during which an nMOS transistor should be in an OFF state, its ON state continues and, therefore, a boosted voltage lowers. For example, in the conventional power supply circuit shown in FIG. 18, for example, when the clock CLKA has the low potential [VSS] and the clock CLKB has the high potential [VDD], the potential at the node N0B is boosted up to the level [2×VDD-Vth] and the potential at the node N1A is boosted up to the level [3×VDD-Vth]. At this time, the condition for which the nMOS transistor MT1B gets into an ON state is that a potential difference (voltage Vgs between the gate and source) between the node N1A connected to a gate electrode and the node N0B connected to a source electrode becomes the voltage [VDD]. On the other hand, when the clock CLKA has the high potential [VDD] and the clock CLKB has the low potential [VSS], the potential at the node N0B lowers to the level [VDD-Vth] at which the nMOS transistor MT5B gets into an ON state.
At this time point, though the potential at the node N1A lowers to the level [2×VDD-Vth], the MOS transistor MT1B, if the voltage Vgs between the gate and source is [VDD=(2×VDD-Vth)−(VDD-Vth)], continues to be in the ON state. Due to this, a current flows from the node N1B to the node N0B, which causes the boosted voltage of the node N1B to be lowered. When the potential at the node N0B is boosted or when lowering of the potential at the node N1A causes a voltage between the node N0B and node N1A to become lower than a threshold voltage of the gate of the nMOS transistor MT1B, the nMOS transistor MT1B gets into an OFF state. Due to this, the power supply circuit (charge-pump circuit) presents a problem that the actual DC output voltage [VOUT] becomes lower than a voltage [6×VDD-Vth], thus causing a decrease in power efficiency.
The reason for this is that a gate signal of each of the nMOS transistors making up the charge pump is not at a level enough to make the nMOS transistor get completely into an OFF state. Generally, the condition for turning on a MOS transistor is that a voltage Vgs between a gate and source ≧VDD>Vth and the condition for turning off the MOS transistor is that Vgs≦0V and a potential of the gate signal at which the nMOS transistor MT1B shown in FIG. 14 gets into the ON state is the potential [3×VDD-Vth] and a potential of a gate signal at which the nMOS transistor MT1B gets into the OFF state is the potential [VDD-Vth]. The gate signal is a signal obtained by increasing the amplitude [VDD] of each of the clocks CLKA and CLKB so as to be the amplitude [2×VDD].
As a circuit to increase the amplitude of a clock, a level shift circuit is available. The display device disclosed in Patent Reference 2 (Japanese Patent Application Laid-open No. 2005-037842, abstract, FIG. 1) includes such a level shift circuit. The disclosed level shift circuit, as shown in FIG. 19, is made up of nMOS transistors MT1L, MT2L, and MT3L. In the disclosed level shift circuit, clocks INA and INB both being opposite in phase to each other and each having a potential [VDD] or [VSS] are input and an expanded signal OUTA obtained by converting a potential level on a high-potential side from the level [VDD] to [VDH] is generated.
Moreover, when the same level shift circuit as the above level shift is to be configured by using pMOS transistors, as the potential of the DC power, the potential of the supply power [VDH] is replaced with the [VSS] and vice versa. On the other hand, in order to process input signals, in the clock having the [VDD] as its high potential and the [VSS] as its low potential, it is necessary that the potentials on the high potential side and on the low potential side are chanted to be the potential [VDH] and to be the potential [VDH-VDD] respectively. The amplitudes of these clocks are the same as those shown in FIG. 19, however, the potential is boosted by a level [VDH-VDD]. This presents a problem in that another signal generating circuit to generate an input signal of the level shift circuit is required.